Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally >1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “optics;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
When under very low k1 lithography imaging, where k1<0.35, and k1 is defined as follows: k1=0.5*(Feature pitch)*(Numerical Aperture)/(Exposure Wavelength), this is equivalent to pattern IC design at below one-half to one-third of the exposure wavelength (λ). For ArF exposure source, at λ=193 nm, the lithography process requires to pattern 90 nm to 65 nm IC features.
Nowadays, to develop a practical lithographic resist process, it is normally first done with using a lithography simulation tool for process optimization. Subsequently, actual wafer printing verification is performed. This helps expedite the develop cycle, reduce the cost, and allow more robust and well-controlled optimization to be performed via simulation. The challenge is how to ensure a resist CD to be predicted with sufficient accuracy when using the simulation tool. Resist model calibration is one of the critical key factors in the simulation process, and the robustness of the simulation model is another important factor.
In a typical lithography simulation, there are three basic steps. The first step is to calculate an aerial image for the feature in question. The aerial image calculation is based on the optical settings of an exposure tool, which include, for example, numerical aperture, exposure wavelength, etc. The aerial image calculation can be performed using known simulation tools, such as MaskTools' LithoCruiser™.
The second step is to perform a post exposure bake (PEB) step. In actual wafer printing where chemically amplified photoresist is used, this step is very important. The step provides two functions: (1) allowing chemical amplification for photo speed to take place due to the heat, and (2) minimize resist CD swing as caused by standing wave effects, this is done by diffusing photo acid generated during the exposure. A diffusion length or range can be in the range from 0 to 50 nm or more.
The third step is to develop a resist pattern based on the diffused aerial image.
For the second and third steps, basically two approaches have been established for lithography simulation. One is to use a first principle PEB model which is followed by another first principle resist develop model. The first principle model had first been proposed by Dill et al. in 1975. In mid 1980's, Lin and Mack separately proposed another form of resist development model, or lumped parameter models (LPM). The approach is to model pattern formation of the photoresist as a lumped parameter system. In a LPM, the resist CD is calculated based on photoresist characteristics such as contrast (gamma), thickness, image threshold, and development rate, etc. For simulation prediction, a LPM resist development model typically convolves with a simplistic diffusion function or kernel. This is essentially to emulate the PEB effect.
The photo resist simulation models based on the first principle is typically much more computationally demanding in terms of calculation. However, notwithstanding the use of such models, it is still difficult to fully account for exactly what occurs during PEB and resist development step. For modern resist systems, it is extremely difficult to use a generic model to represent exactly the chemical reaction behavior for different photoresist formulation. The first principle model suffers from the following drawbacks when it comes to very low k1 imaging: less than satisfactory resist critical dimension (CD) prediction, and prolonged calculation time due to more complicated equations.
The LPM for resist CD prediction can be very fast with respect to processing time because fewer numbers of lumped parameters are required for the calculation. Traditionally, the industry's impression has been that the resist CD prediction is less accurate due to lumped and often much simplified parameters being utilized. In recent years, however, due to the difficulty to timely develop resist formulation specific physical models; more attention has been given to the LPM for improved accuracy. One key is to convolve the LPM with a sophisticated linear diffusion function or kernel. In the past, the linear diffusion kernel is single Gaussian function with a given width.
Brunner et al. has proposed sub-nm precision CD prediction that is comparable or better than the physical resist models in an article T. Brunner et al., Impact of resist blur on MEF, OPC and CD control, 2004 SPIE conference, 2004, the entirety of which is incorporated herein by reference. In Brunner's work, the use of multiple Gaussian diffusion kernels with the same diffusion lengths in different directions (“circular form,” or “spherical form” when considered in 3-dimension, see FIG. 4A) has been considered as image “blur” functions, or the modulation transfer functions (MTF). As explained by Brunner, tuning the lengths for each of Gaussian kernels, or the respective MTF's, as a means of calibration, accurate resist CD can be predicted together with a subsequent LPM.
However, in Brunner et al., the Gaussian diffusion kernels utilized in the simulation process all have the same diffusion lengths in the different directions (“circular form,” or “spherical form”). As explained further below, this leads to limitations in resist CD calibration. It is one object of the present invention to provide a simulation process which overcomes these limitations.